1. Field
This disclosure relates to semiconductor memory devices.
2. Description of Related Art
In a semiconductor memory device provided with SRAM (static random access memory) and the like, for example, a timing signal of a sense amplifier is generated to amplify read data from a memory cell, or data is written to generate a timing signal of a write amplifier.
When reading data from a memory cell in the above-mentioned semiconductor memory device, the time required to read data from the memory cell through the bit line is extended as the length of a bit line becomes longer.
When writing data in a memory cell, in contrast, the time required to write data in a memory cell is determined by the time required to finish writing data in the memory cell after applying write data to a bit line.
In the above mentioned semiconductor memory device, the time required to read data from a memory cell changes depending on a bit line length. Therefore, in case of a comparatively short bit line length, when the time to write data in a memory cell is set to be equal to the time to read data from a memory cell, it may become impossible to set sufficient write time to write data in a memory cell. Consequently, in order to optimally conduct data reading from a memory cell or data writing in a memory cell, data read time or data write time has to be set individually.
Japanese Laid-open Patent Publication No. 2006-4476 discloses a semiconductor memory device provided with: a first replica bit line consisting of wiring of the same wiring width and wiring interval as those of a bit line in a memory cell array and generating a read timing signal; and a second replica bit line comprising wiring of the same wiring width and wiring interval as those of a bit line and generating a write timing signal.
In the semiconductor memory device of Japanese Laid-open Patent Publication No. 2006-4476, the first replica bit line and the second replica bit line generate a read timing signal and a write timing signal respectively and control the serial operational timing of read and write, and enable the high-speed serial operation of read and write.